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» Formal Methods for Networks on Chips
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TKDE
2012
487views Formal Methods» more  TKDE 2012»
13 years 1 months ago
Query Planning for Continuous Aggregation Queries over a Network of Data Aggregators
—Continuous queries are used to monitor changes to time varying data and to provide results useful for online decision making. Typically a user desires to obtain the value of som...
Rajeev Gupta, Krithi Ramamritham
ICCAD
2005
IEEE
108views Hardware» more  ICCAD 2005»
15 years 8 months ago
A routing algorithm for flip-chip design
— The flip-chip package gives the highest chip density of any packaging method to support the pad-limited Application-Specific Integrated Circuit (ASIC) designs. In this paper,...
Jia-Wei Fang, I-Jye Lin, Ping-Hung Yuh, Yao-Wen Ch...
FPL
2005
Springer
226views Hardware» more  FPL 2005»
15 years 4 months ago
A Parallel MPEG-4 Encoder for FPGA Based Multiprocessor SoC
A parallel MPEG-4 Simple Profile encoder for FPGA based multiprocessor System-on-Chip (SOC) is presented. The goal is a computationally scalable framework independent of platform....
Olli Lehtoranta, Erno Salminen, Ari Kulmala, Marko...
ASPDAC
2009
ACM
159views Hardware» more  ASPDAC 2009»
15 years 4 months ago
Congestion-aware power grid optimization for 3D circuits using MIM and CMOS decoupling capacitors
— In three-dimensional (3D) chips, the amount of supply current per package pin is significantly more than in two-dimensional (2D) designs. Therefore, the power supply noise pro...
Pingqiang Zhou, Karthikk Sridharan, Sachin S. Sapa...
TCAD
2008
92views more  TCAD 2008»
14 years 10 months ago
IP Watermarking Using Incremental Technology Mapping at Logic Synthesis Level
Abstract--This paper proposes an adaptive watermarking technique by modulating some closed cones in an originally optimized logic network (master design) for technology mapping. Th...
Aijiao Cui, Chip-Hong Chang, Sofiène Tahar