531 search results - page 7 / 107 » Formal Methods for Networks on Chips |
FMCAD
2008
Springer
14 years 11 months ago
2008
Springer
Post-silicon debug is the problem of determining what's wrong when the fabricated chip of a new design behaves incorrectly. This problem now consumes over half of the overall ...
ISVLSI
2006
IEEE
15 years 3 months ago
2006
IEEE
Network-on-Chip (NoC) proposes networks to replace buses as a scalable global communication interconnect for future SoC designs. However, a bus is very efficient in broadcasting....
TCAD
2010
14 years 4 months ago
2010
The structural redundancy inherent to on-chip interconnection networks [networks on chip (NoC)] can be exploited by adaptive routing algorithms in order to provide connectivity eve...
SBCCI
2003
ACM
15 years 2 months ago
2003
ACM
Network on Chip (NoC) is a new paradigm for designing core based System on Chips. It supports high degree of reusability and is scalable. In this paper, an efficient Two-Step Gene...
83
Voted
SAMOS
2005
Springer
15 years 3 months ago
2005
Springer
The performance and area of a System-on-Chip depend on the utilized communication method. This paper presents simulation-based comparison of generic, synthesizable single bus, hie...