531 search results - page 9 / 107 » Formal Methods for Networks on Chips |
EUROPAR
2010
Springer
14 years 9 months ago
2010
Springer
Abstract. Current trends in CMPs indicate that the core count will increase in the near future. One of the main performance limiters of these forthcoming microarchitectures is the ...
67
Voted
DAC
1998
ACM
15 years 10 months ago
1998
ACM
This paper presents a method for power and ground (p/g) network routing for high speed CMOS chips with multiple p/g pads. Our objective is not to reduce the total amount of the gr...
58
Voted
SFM
2005
Springer
15 years 3 months ago
2005
Springer
IJIT
2004
14 years 11 months ago
2004
As computer network technology becomes increasingly complex, it becomes necessary to place greater requirements on the validity of developing standards and the resulting technology...
DFT
2009
IEEE
15 years 4 months ago
2009
IEEE
We propose a framework that allows dual-layer cooperative error control in a nanoscale network-on-chip (NoC), to simultaneously improve reliability, performance and energy efficie...