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FORMATS
2006
Springer
15 years 7 months ago
Verification of the Generic Architecture of a Memory Circuit Using Parametric Timed Automata
Using a variant of Clariso-Cortadella's parametric method for verifying asynchronous circuits, we formally derive a set of linear constraints that ensure the correctness of so...
Remy Chevallier, Emmanuelle Encrenaz-Tiphèn...
POPL
2005
ACM
16 years 4 months ago
Formal prototyping in early stages of protocol design
Network protocol design is usually an informal process where debugging is based on successive iterations of a prototype implementation. The feedback provided by a prototype can be...
Alwyn Goodloe, Carl A. Gunter, Mark-Oliver Stehr
UML
2005
Springer
15 years 9 months ago
A Formal Enforcement Framework for Role-Based Access Control Using Aspect-Oriented Programming
Many of today’s software applications require a high-level of security, defined by a detailed policy and attained via mechanisms such as role-based access control (RBAC), mandat...
Jaime A. Pavlich-Mariscal, Laurent Michel, Steven ...
FMCAD
2006
Springer
15 years 7 months ago
Enabling Large-Scale Pervasive Logic Verification through Multi-Algorithmic Formal Reasoning
Pervasive Logic is a broad term applied to the variety of logic present in hardware designs, yet not a part of their primary functionality. Examples of pervasive logic include init...
Tilman Glökler, Jason Baumgartner, Devi Shanm...
FMICS
2010
Springer
15 years 4 months ago
SMT-Based Formal Verification of a TTEthernet Synchronization Function
Abstract. TTEthernet is a communication infrastructure for mixedcriticality systems that integrates dataflow from applications with different criticality levels on a single network...
Wilfried Steiner, Bruno Dutertre