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ICCAD
2008
IEEE
125views Hardware» more  ICCAD 2008»
16 years 26 days ago
A succinct memory model for automated design debugging
— In today’s complex SoC designs, verification and debugging are becoming ever more crucial and increasingly timeconsuming tasks. The prevalence of embedded memories adds to t...
Brian Keng, Hratch Mangassarian, Andreas G. Veneri...
VMCAI
2010
Springer
15 years 11 months ago
Regular Linear Temporal Logic with Past
This paper upgrades Regular Linear Temporal Logic (RLTL) with past operators and complementation. RLTL is a temporal logic that extends the expressive power of linear temporal logi...
César Sánchez, Martin Leucker
CHI
2010
ACM
15 years 10 months ago
Understanding usability practices in complex domains
Although usability methods are widely used for evaluating conventional graphical user interfaces and websites, there is a growing concern that current approaches are inadequate fo...
Parmit K. Chilana, Jacob O. Wobbrock, Andrew J. Ko
CC
2010
Springer
117views System Software» more  CC 2010»
15 years 10 months ago
Punctual Coalescing
Compilers use register coalescing to avoid generating code for copy instructions. For architectures with register aliasing such as x86, Smith, Ramsey, and Holloway (2004) presented...
Fernando Magno Quintão Pereira, Jens Palsbe...
131
Voted
ATS
2009
IEEE
142views Hardware» more  ATS 2009»
15 years 10 months ago
Speeding up SAT-Based ATPG Using Dynamic Clause Activation
Abstract—SAT-based ATPG turned out to be a robust alternative to classical structural ATPG algorithms such as FAN. The number of unclassified faults can be significantly reduce...
Stephan Eggersglüß, Daniel Tille, Rolf ...