Sciweavers

478 search results - page 19 / 96
» Formal Methods for Specifying, Validating, and Verifying Req...
Sort
View
ESORICS
2004
Springer
15 years 3 months ago
A Formalization of Anonymity and Onion Routing
The use of formal methods to verify security protocols with respect to secrecy and authentication has become standard practice. In contrast, the formalization of other security goa...
Sjouke Mauw, Jan Verschuren, Erik P. de Vink
FM
2001
Springer
96views Formal Methods» more  FM 2001»
15 years 2 months ago
Houdini, an Annotation Assistant for ESC/Java
A static program checker that performs modular checking can check one program module for errors without needing to analyze the entire program. Modular checking requires that each m...
Cormac Flanagan, K. Rustan M. Leino
ECBS
2005
IEEE
58views Hardware» more  ECBS 2005»
15 years 3 months ago
MoDeII: Modeling and Analyzing Time-Constraints
The fulfillment of time requirements is one of the major acceptance criteria of safety-critical and real-time systems. They are dictated by the environment of these systems and a...
Jewgenij Botaschanjan, Jan Jürjens
93
Voted
ENTCS
2006
176views more  ENTCS 2006»
14 years 9 months ago
Gauss: A Framework for Verifying Scientific Computing Software
High performance scientific computing software is of critical international importance as it supports scientific explorations and engineering. Software development in this area is...
Robert Palmer, Steve Barrus, Yu Yang, Ganesh Gopal...
CORR
2010
Springer
176views Education» more  CORR 2010»
14 years 9 months ago
Bus Protocols: MSC-Based Specifications and Translation into Program of Verification Tool for Formal Verification
Message Sequence Charts (MSCs) are an appealing visual formalism mainly used in the early stages of system design to capture the system requirements. However, if we move towards a...
Kamrul Hasan Talukder