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» Formal Modeling and Analysis of Organizations
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ANSS
2000
IEEE
15 years 3 months ago
Using the DEVS Paradigm to Implement a Simulated Processor
This work is devoted to present the design and implementation of Alfa-1, a simulated computer with educational purposes. The DEVS formalism was used to attack the complexity of th...
Sergio Daicz, Alejandro Troccoli, Sergio Zlotnik, ...
DATE
2008
IEEE
106views Hardware» more  DATE 2008»
15 years 6 months ago
Modeling Event Stream Hierarchies with Hierarchical Event Models
Compositional Scheduling Analysis couples local scheduling analysis via event streams. While local analysis has successfully been extended to include hierarchical scheduling strat...
Jonas Rox, Rolf Ernst
VLSID
2001
IEEE
129views VLSI» more  VLSID 2001»
15 years 12 months ago
Design Of Provably Correct Storage Arrays
In this paper we describe a hardware design method for memory and register arrays that allows the application of formal equivalence checking for comparing a high-level register tr...
Rajiv V. Joshi, Wei Hwang, Andreas Kuehlmann
FORMATS
2007
Springer
15 years 3 months ago
Combining Formal Verification with Observed System Execution Behavior to Tune System Parameters
Resource limited DRE (Distributed Real-time Embedded) systems can benefit greatly from dynamic adaptation of system parameters. We propose a novel approach that employs iterative t...
Minyoung Kim, Mark-Oliver Stehr, Carolyn L. Talcot...
93
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MEMOCODE
2003
IEEE
15 years 4 months ago
MoDe: A Method for System-Level Architecture Evaluation
System-level design methodologies for embedded HW/SW systems face several challenges: In order to be susceptible to systematic formal analysis based on state-space exploration, a ...
Jan Romberg, Oscar Slotosch, Gabor Hahn