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FDL
2004
IEEE
15 years 7 months ago
A Formal Verification Approach for IP-based Designs
This paper proposes a formal verification methodology which is smoothly integrated with component-based system-level design, using a divide and conquer approach. The methodology a...
Daniel Karlsson, Petru Eles, Zebo Peng
143
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RULEML
2009
Springer
15 years 10 months ago
Correlating Business Events for Event-Triggered Rules
Abstract. Event processing rules may be prescribed in many different ways, including by finite state machines, graphical methods, ECA (event-conditionaction) rules or reactive rule...
Josef Schiefer, Hannes Obweger, Martin Suntinger
COLING
2010
14 years 10 months ago
Finite-state Scriptural Translation
We use robust and fast Finite-State Machines (FSMs) to solve scriptural translation problems. We describe a phonetico-morphotactic pivot UIT (universal intermediate transcription)...
M. G. Abbas Malik, Christian Boitet, Pushpak Bhatt...
144
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FM
2009
Springer
169views Formal Methods» more  FM 2009»
15 years 7 months ago
Model Checking Linearizability via Refinement
Abstract. Linearizability is an important correctness criterion for implementations of concurrent objects. Automatic checking of linearizability is challenging because it requires ...
Yang Liu 0003, Wei Chen, Yanhong A. Liu, Jun Sun 0...
143
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APIN
2002
121views more  APIN 2002»
15 years 3 months ago
Applying Learning by Examples for Digital Design Automation
This paper describes a new learning by example mechanism and its application for digital circuit design automation. This mechanism uses finite state machines to represent the infer...
Ben Choi