Finding flaws in security protocol implementations is hard. Finding flaws in the implementations of sensor network security protocols is even harder because they are designed to p...
As VLSI fabrication technology progresses to 65nm feature sizes and smaller, transistors no longer operate as ideal switches. This motivates verifying digital circuits using contin...
We present a tool-supported approach to the validation of system-level timing properties in formal models of distributed real-time embedded systems. Our aim is to provide system a...
John S. Fitzgerald, Simon Tjell, Peter Gorm Larsen...
Abstract. Symbolic state-space generators are notoriously hard to parallelise. However, the Saturation algorithm implemented in the SMART verification tool differs from other seque...
Abstract: Event-driven Process Chains (EPCs) are a commonly used modelling technique for design and documentation of business processes. Although EPCs have an easy-to-understand no...