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» Formal Models for Embedded System Design
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ECRTS
2007
IEEE
15 years 1 months ago
The Space of EDF Feasible Deadlines
It is well known that the performance of computer controlled systems is heavily affected by delays and jitter occurring in the control loops, which are mainly caused by the interf...
Enrico Bini, Giorgio C. Buttazzo
LCTRTS
2004
Springer
15 years 3 months ago
Flattening statecharts without explosions
We present a polynomial upper bound for flattening of UML statecharts. An efficient flattening technique is derived and implemented in SCOPE—a code generator targeting constra...
Andrzej Wasowski
DATE
2009
IEEE
90views Hardware» more  DATE 2009»
15 years 4 months ago
Property analysis and design understanding
—Verification is a major issue in circuit and system design. Formal methods like bounded model checking (BMC) can guarantee a high quality of the verification. There are severa...
Ulrich Kühne, Daniel Große, Rolf Drechs...
DATE
2008
IEEE
106views Hardware» more  DATE 2008»
15 years 4 months ago
Modeling Event Stream Hierarchies with Hierarchical Event Models
Compositional Scheduling Analysis couples local scheduling analysis via event streams. While local analysis has successfully been extended to include hierarchical scheduling strat...
Jonas Rox, Rolf Ernst
DAC
1998
ACM
15 years 2 months ago
A Tool for Performance Estimation of Networked Embedded End-systems
Networked embedded systems are expected to support adaptive streaming audio/video applications with soft real-time constraints. These systems can be designed in a cost efficient ...
Asawaree Kalavade, Pratyush Moghé