289 search results - page 15 / 58 » Formal Verification in a Commercial Setting |
114
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FMCAD
1998
Springer
15 years 4 months ago
1998
Springer
We present a new approach to the verification of hardware systems with data dependencies using temporal logic symbolic model checking. As a benchmark we take Tomasulo's algori...
105
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FORMATS
2009
Springer
15 years 3 months ago
2009
Springer
Probabilistic timed automata (PTAs) are used for formal modelling and verification of systems with probabilistic, nondeterministic and real-time behaviour. For non-probabilistic ti...
102
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CIIA
2009
15 years 26 days ago
2009
Abstract. Formal verification of digital systems is achieved, today, using one of two main approaches: states exploration (mainly model checking and equivalence checking) or deduct...
FUIN
2006
14 years 11 months ago
2006
Abstract. This paper describes an attempt to combine theorem proving and model-checking to formally verify real-time systems in a discrete time setting. The Timed Automata Modeling...
DAC
2010
ACM
15 years 3 months ago
2010
ACM
Timing exception verification has become a center of interest as incorrect constraints can lead to chip failures. Proving that a false path is valid or not is a difficult problem ...