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» Formal Verification in a Commercial Setting
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SIGSOFT
2009
ACM
15 years 10 months ago
Probabilistic environments in the quantitative analysis of (non-probabilistic) behaviour models
System specifications have long been expressed through automata-based languages, enabling verification techniques such as model checking. These verification techniques can assess ...
Esteban Pavese, Sebastián Uchitel, Ví...
ECCB
2008
IEEE
14 years 9 months ago
Temporal logic patterns for querying dynamic models of cellular interaction networks
Abstract: Models of the dynamics of cellular interaction networks have become increasingly larger in recent years. Formal verification based on model checking provides a powerful t...
Pedro T. Monteiro, Delphine Ropers, Radu Mateescu,...
POPL
2004
ACM
15 years 10 months ago
A bisimulation for dynamic sealing
We define seal, an untyped call-by-value -calculus with primitives for protecting abstract data by sealing, and develop a bisimulation proof method that is sound and complete with...
Eijiro Sumii, Benjamin C. Pierce
DAC
1994
ACM
15 years 1 months ago
Error Diagnosis for Transistor-Level Verification
This paper describes a diagnosis technique for locating design errors in circuit implementations which do not match their functional specification. The method efficiently propagat...
Andreas Kuehlmann, David Ihsin Cheng, Arvind Srini...
85
Voted
TCAD
2002
121views more  TCAD 2002»
14 years 9 months ago
Robust Boolean reasoning for equivalence checking and functional property verification
Many tasks in CAD, such as equivalence checking, property checking, logic synthesis, and false paths analysis require efficient Boolean reasoning for problems derived from circuits...
Andreas Kuehlmann, Viresh Paruthi, Florian Krohm, ...