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» Formal Verification in a Commercial Setting
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CAV
1990
Springer
114views Hardware» more  CAV 1990»
15 years 1 months ago
Formal Verification of Digital Circuits Using Symbolic Ternary System Models
Ternary system modeling involves extending the traditional set of binary values
Randal E. Bryant, Carl-Johan H. Seger
ASIAN
2006
Springer
118views Algorithms» more  ASIAN 2006»
15 years 1 months ago
An Approach to Formal Verification of Arithmetic Functions in Assembly
Abstract. It is customary to write performance-critical parts of arithmetic functions in assembly: this enables finely-tuned algorithms that use specialized processor instructions....
Reynald Affeldt, Nicolas Marti
ICCD
2000
IEEE
119views Hardware» more  ICCD 2000»
15 years 1 months ago
Source-Level Transformations for Improved Formal Verification
A major obstacle to widespread acceptance of formal verification is the difficulty in using the tools effectively. Although learning the basic syntax and operation of a formal ver...
Brian D. Winters, Alan J. Hu
DSD
2002
IEEE
102views Hardware» more  DSD 2002»
15 years 2 months ago
Formal Verification of a DSP Chip Using an Iterative Approach
In this paper we describe a methodology for the formal verification of a DSP chip using the HOL theorem prover. We used an iterative method to specify both the behavioral and stru...
Ali Habibi, Sofiène Tahar, Adel Ghazel
97
Voted
DAC
1997
ACM
15 years 1 months ago
Formal Verification of a Superscalar Execution Unit
Abstract. Many modern systems are designed as a set of interconnected reactive subsystems. The subsystem verification task is to verify an implementation of the subsystem against t...
Kyle L. Nelson, Alok Jain, Randal E. Bryant