714 search results - page 93 / 143 » Formal Verification of Cognitive Models |
192
Voted
CODES
2008
IEEE
15 years 8 months ago
2008
IEEE
SystemC is widely used for modeling and simulation in hardware/software co-design. Due to the lack of a complete formal semantics, it is not possible to verify SystemC designs. In...
168
Voted
CAV
2006
Springer
15 years 10 months ago
2006
Springer
We present an approach for applying symmetry reduction techniques to probabilistic model checking, a formal verification method for the quantitative analysis of systems with stocha...
179
Voted
DAC
2007
ACM
15 years 10 months ago
2007
ACM
When designers create RTL models from a system-level specification, arrays in the system-level model are often implemented as memories in the RTL. Knowing the correspondence betwe...
158
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SIGSOFT
2005
ACM
16 years 6 months ago
2005
ACM
Online testing is a technique in which test derivation from a model program and test execution are combined into a single algorithm. We describe a practical online testing algorit...
130
Voted
HPCA
2002
IEEE
16 years 6 months ago
2002
IEEE
Several studies of speculative execution based on values have reported promising performance potential. However, virtually all microarchitectures in these studies were described i...