858 search results - page 103 / 172 » Formal Verification of Digital Systems |
108
Voted
SPIN
2000
Springer
15 years 2 months ago
2000
Springer
The Temporal Rover is a specification based verification tool for applications written in C, C++, Java, Verilog and VHDL. The tool combines formal specification, using Linear-Time ...
ISSS
2002
IEEE
15 years 4 months ago
2002
IEEE
ForSyDe (FORmal SYstem DEsign) is a methodology which addresses the design of SoC applications which may contain control as well as data flow dominated parts. Starting with a for...
DIM
2008
ACM
15 years 25 days ago
2008
ACM
Public-key based certificates provide a standard way to prove one's identity, as attested by some certificate authority (CA). However, plain certificates provide a binary ide...
SAS
2009
Springer
15 years 11 months ago
2009
Springer
ion Refinement for Quantified Array Assertions Mohamed Nassim Seghir1, , Andreas Podelski1 , and Thomas Wies1,2 1 University of Freiburg, Germany 2 EPFL, Switzerland Abstract. We p...
DATE
2005
IEEE
15 years 4 months ago
2005
IEEE
Automated synthesis of monitors from high-level properties plays a significant role in assertion-based verification. We present here a methodology to synthesize assertion monitors...