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» Formal Verification of Digital Systems
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DATE
2009
IEEE
115views Hardware» more  DATE 2009»
15 years 3 months ago
Customizing IP cores for system-on-chip designs using extensive external don't-cares
Traditional digital circuit synthesis flows start from an HDL behavioral definition and assume that circuit functions are almost completely defined, making don't-care conditio...
Kai-Hui Chang, Valeria Bertacco, Igor L. Markov
ENTCS
2006
137views more  ENTCS 2006»
14 years 11 months ago
An Efficient Method for Computing Exact State Space of Petri Nets With Stopwatches
In this paper, we address the issue of the formal verification of real-time systems in the context of a preemptive scheduling policy. We propose an algorithm which computes the st...
Morgan Magnin, Didier Lime, Olivier H. Roux
CADE
2007
Springer
15 years 11 months ago
Symbolic Fault Injection
Fault tolerance mechanisms are a key ingredient of dependable systems. In particular, software-implemented hardware fault tolerance (SIHFT) is gaining in popularity, because of its...
Daniel Larsson, Reiner Hähnle
77
Voted
PPOPP
2010
ACM
15 years 8 months ago
Featherweight X10: a core calculus for async-finish parallelism
We present a core calculus with two of X10's key constructs for parallelism, namely async and finish. Our calculus forms a convenient basis for type systems and static analys...
Jonathan K. Lee, Jens Palsberg
ISQED
2000
IEEE
131views Hardware» more  ISQED 2000»
15 years 3 months ago
Low Power Testing of VLSI Circuits: Problems and Solutions
Power and energy consumption of digital systems may increase significantly during testing. This extra power consumption due to test application may give rise to severe hazards to ...
Patrick Girard