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» Formal Verification of Digital Systems
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POPL
2005
ACM
16 years 2 months ago
Context logic and tree update
Spatial logics have been used to describe properties of treelike structures (Ambient Logic) and in a Hoare style to reason about dynamic updates of heap-like structures (Separatio...
Cristiano Calcagno, Philippa Gardner, Uri Zarfaty
PASTE
2004
ACM
15 years 7 months ago
Validation of assembler programs for DSPs: a static analyzer
Digital Signal Processors are widely used in critical embedded systems to pilot low-level, often critical functionalities. We describe a static analyzer based on abstract interpre...
Matthieu Martel
DBSEC
2007
87views Database» more  DBSEC 2007»
15 years 3 months ago
Towards a Times-Based Usage Control Model
Abstract. Modern information systems require temporal and privilegeconsuming usage of digital objects. To meet these requirements, we present a new access control model–Times-bas...
Baoxian Zhao, Ravi S. Sandhu, Xinwen Zhang, Xiaoli...
VLSID
2002
IEEE
189views VLSI» more  VLSID 2002»
16 years 2 months ago
Automatic Modeling and Validation of Pipeline Specifications Driven by an Architecture Description Language
Verification is one of the most complex and expensive tasks in the current Systems-on-Chip (SOC) design process. Many existing approaches employ a bottom-up approach to pipeline v...
Prabhat Mishra, Hiroyuki Tomiyama, Ashok Halambi, ...
ICSE
2004
IEEE-ACM
16 years 2 months ago
Verifying DAML+OIL and Beyond in Z/EVES
Semantic Web, the next generation of Web, gives data well-defined and machine-understandable meaning so that they can be processed by remote intelligent agents cooperatively. Onto...
Jin Song Dong, Chew Hung Lee, Yuan-Fang Li, Hai H....