858 search results - page 23 / 172 » Formal Verification of Digital Systems |
95
Voted
SIGSOFT
2007
ACM
15 years 11 months ago
2007
ACM
Model checking techniques have traditionally dealt with temporal logic languages and automata interpreted over -words, i.e., infinite in the future but finite in the past. However...
TCAD
2008
14 years 10 months ago
2008
The quality and the correctness of software is often the greatest concern in electronic systems. Formal verification tools can provide a guarantee that a design is free of specific...
106
Voted
AINA
2003
IEEE
15 years 1 months ago
2003
IEEE
Condition Data Flow Diagrams (CDFDs) are a formalized notation resulting from the integration of Yourdon Data Flow Diagrams, Petri Nets, and pre-post notation. They are used in th...
104
Voted
IJCSA
2006
14 years 10 months ago
2006
The Dynamic Host Configuration Protocol (DHCP) is a widely used communication protocol. In this paper, a portion of the protocol is chosen for modeling and verification, namely th...
91
Voted
ICCS
2007
Springer
15 years 4 months ago
2007
Springer
Dynamic reconfigurable simulation based on Discrete Event System Specification (DEVS) requires efficient verification of simulation models. Traditional verification method of DEVS ...