858 search results - page 24 / 172 » Formal Verification of Digital Systems |
74
Voted
IJIT
2004
14 years 11 months ago
2004
As computer network technology becomes increasingly complex, it becomes necessary to place greater requirements on the validity of developing standards and the resulting technology...
ICCAD
1994
IEEE
15 years 2 months ago
1994
IEEE
Language containment is a method for design verification that involves checking if the behavior of the system to be verified is a subset of the behavior of the specifications (pro...
SECURWARE
2007
IEEE
15 years 4 months ago
2007
IEEE
The paper discusses an experience in using a realtime UML/SysML profile and a formal verification toolkit to check a secure group communication system against temporal requirement...
123
Voted
CCECE
2006
IEEE
15 years 4 months ago
2006
IEEE
To help programmers of high-performance computing (HPC) systems avoid communication-related errors, we employ a formal process algebra, Communicating Sequential Processes (CSP), w...
91
Voted
CAI
2006
Springer
14 years 10 months ago
2006
Springer
In this paper, formal verification methodologies and the SPR (Safety Problem Resolver) model checking tool are used for verifying a security model's safety. The SPR tool makes...