858 search results - page 25 / 172 » Formal Verification of Digital Systems |
87
Voted
ICSE
2009
IEEE-ACM
14 years 8 months ago
2009
IEEE-ACM
This paper presents experiments realized by Airbus on model checking a safety critical system, lessons learnt and ways forward to extend the industrial use of formal verification ...
77
Voted
CSREAESA
2004
14 years 11 months ago
2004
In this paper we present an algorithm for automatic extraction of system behavior from a structural Verilog specification. The algorithm generates a series-parallel poset expressi...
77
Voted
RTS
2008
14 years 9 months ago
2008
The aim of this paper is to show, how a multitasking application running under a real-time operating system compliant with an OSEK/VDX standard can be modeled by timed automata. Th...
79
Voted
ATVA
2007
Springer
15 years 2 months ago
2007
Springer
One of the prerequisites for information society is secure and reliable communication among computing systems. Accordingly, network security appliances become key components of inf...
82
Voted
ASPDAC
2004
ACM
15 years 2 months ago
2004
ACM
The design of complex systems is largely ruled by the time needed for verification. Even though formal methods can provide higher reliability, in practice often simulation based ve...