858 search results - page 30 / 172 » Formal Verification of Digital Systems |
FMSD
2000
14 years 10 months ago
2000
We review a number of formal verification techniques supported by STeP, the Stanford Temporal Prover, describing how the tool can be used to verify properties of several versions o...
CODES
2005
IEEE
15 years 4 months ago
2005
IEEE
The continuous improvement on the design methodologies and processes has made possible the creation of huge and very complex digital systems. Design verification is one of the mai...
ENTCS
2010
14 years 7 months ago
2010
We propose an automata-based formalism for the description of biological systems that allows properties expressed in the universal fragment of CTL to be verified in a modular way....
102
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FORMATS
2004
Springer
15 years 2 months ago
2004
Springer
We discuss the modeling and verification of real-time systems using the SAL model checker. A new modeling framework based on event calendars enables dense timed systems to be descr...
100
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FLAIRS
2000
14 years 11 months ago
2000
This paper presents a formal security policy model for SmartCards with digital signature application. This kind of model is necessary for each evaluation according to Information ...