Sciweavers

858 search results - page 58 / 172
» Formal Verification of Digital Systems
Sort
View
CAV
2009
Springer
209views Hardware» more  CAV 2009»
15 years 11 months ago
Static and Precise Detection of Concurrency Errors in Systems Code Using SMT Solvers
Context-bounded analysis is an attractive approach to verification of concurrent programs. Bounding the number of contexts executed per thread not only reduces the asymptotic compl...
Shuvendu K. Lahiri, Shaz Qadeer, Zvonimir Rakamari...
89
Voted
VLSID
2006
IEEE
192views VLSI» more  VLSID 2006»
15 years 4 months ago
Beyond RTL: Advanced Digital System Design
This tutorial focuses on advanced techniques to cope with the complexity of designing modern digital chips which are complete systems often containing multiple processors, complex...
Shiv Tasker, Rishiyur S. Nikhil
FMAM
2010
157views Formal Methods» more  FMAM 2010»
14 years 8 months ago
An Experience on Formal Analysis of a High-Level Graphical SOA Design
: In this paper, we present the experience gained with the participation in a case study in which a novel high-level design language (UML4SOA) was used to produce a service-oriente...
Maurice H. ter Beek, Franco Mazzanti, Aldi Sulova
CAV
1998
Springer
147views Hardware» more  CAV 1998»
15 years 3 months ago
Verification of an Implementation of Tomasulo's Algorithm by Compositional Model Checking
An implementation of an out-of-order processing unit based on Tomasulo's algorithm is formally verified using compositional model checking techniques. This demonstrates that f...
Kenneth L. McMillan
FORMATS
2006
Springer
15 years 2 months ago
Temporal Logic Verification Using Simulation
In this paper, we consider a novel approach to the temporal logic verification problem of continuous dynamical systems. Our methodology has the distinctive feature that enables the...
Georgios E. Fainekos, Antoine Girard, George J. Pa...