Sciweavers

858 search results - page 60 / 172
» Formal Verification of Digital Systems
Sort
View
UML
2004
Springer
15 years 11 months ago
System-on-Chip Verification Process Using UML
Abstract. In this paper, we propose a verification methodology for System-OnChip (SoC) design using Unified Modeling Language (UML). We introduce UML as a formal model to analyze a...
Qiang Zhu, Tsuneo Nakata, Masataka Mine, Kenichiro...
SAC
2008
ACM
15 years 5 months ago
A framework for performance evaluation and functional verification in stochastic process algebras
Despite its relatively short history, a wealth of formalisms exist for algebraic specification of stochastic systems. The goal of this paper is to give such formalisms a unifying ...
Hossein Hojjat, Mohammad Reza Mousavi, Marjan Sirj...
ECRTS
1998
IEEE
15 years 10 months ago
Tool-supported hierarchical design of distributed real-time systems
In this paper we demonstrate the usage of a formal description technique for real-time systems called PLCAutomaton [4] by applying this method to a real-world case study. To this ...
Henning Dierks, Josef Tapken
AGTIVE
2007
Springer
15 years 10 months ago
Verification and Synthesis of OCL Constraints Via Topology Analysis
On the basis of a case-study, we demonstrate the usefulness of topology invariants for model-driven systems development. Considering a graph grammar semantics for a relevant fragme...
Jörg Bauer, Werner Damm, Tobe Toben, Bernd We...
FMCAD
1998
Springer
15 years 10 months ago
Combining Symbolic Model Checking with Uninterpreted Functions for Out-of-Order Processor Verification
We present a new approach to the verification of hardware systems with data dependencies using temporal logic symbolic model checking. As a benchmark we take Tomasulo's algori...
Sergey Berezin, Armin Biere, Edmund M. Clarke, Yun...