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» Formal Verification of Digital Systems
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FORMATS
2007
Springer
15 years 2 months ago
Partial Order Reduction for Verification of Real-Time Components
Abstract. We describe a partial order reduction technique for a realtime component model. Components are described as timed automata with data ports, which can be composed in stati...
John Håkansson, Paul Pettersson
POPL
2008
ACM
15 years 11 months ago
Enhancing modular OO verification with separation logic
Conventional specifications for object-oriented (OO) programs must adhere to behavioral subtyping in support of class inheritance and method overriding. However, this requirement ...
Wei-Ngan Chin, Cristina David, Huu Hai Nguyen, She...
DGO
2003
85views Education» more  DGO 2003»
15 years 9 days ago
Trust Resource Management in Digital Government Through Process Modeling
This paper explores the use of process technology to create formal process models to increase the level of trust that stakeholders have in digital government. Digital Government s...
Lee Osterwil, Norman K. Sondheimer, Anthony Butter...
WSC
1998
15 years 8 days ago
Validation and Verification of the Simulation Model of a Photolithography Process in Semiconductor Manufacturing
Simulation modeling provides an effective and powerful approach for capturing and analyzing complex manufacturing systems. More and more decisions are based on computer generated ...
Nirupama Nayani, Mansooreh Mollaghasemi
69
Voted
AEI
1999
60views more  AEI 1999»
14 years 10 months ago
Rule-base content verification using a digraph-based modelling approach
Ensuring that the content of a rule-base, which is being encoded, is free from problems of consistency, completeness, and conciseness, is necessary to avoid any performance errors...
G. S. Gursaran, S. Kanungo, A. K. Sinha