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» Formal Verification of Digital Systems
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ISQED
2003
IEEE
113views Hardware» more  ISQED 2003»
15 years 3 months ago
Using Integer Equations for High Level Formal Verification Property Checking
This paper describes the use of integer equations for high level modeling digital circuits for application of formal verification properties at this level. Most formal verificatio...
Bijan Alizadeh, Mohammad Reza Kakoee
FDL
2007
IEEE
15 years 2 months ago
Towards Assertion Based Verification of Analog and Mixed Signal Designs Using PSL
Abstract-- Analog and Mixed Signal (AMS) designs are important integrated systems that link digital circuits to the analog world. Following the success of PSL verification methodol...
Ghiath Al Sammane, Mohamed H. Zaki, Zhi Jie Dong, ...
ICFP
2003
ACM
15 years 10 months ago
A formalization of an Ordered Logical Framework in Hybrid with applications to continuation machines
We report on work in progress devoted to the formalization of an Ordered Logical Framework (OLF) based on a two-level architecture [8] in the Hybrid system. OLF here is a second-or...
Alberto Momigliano, Jeff Polakow
ENTCS
2006
125views more  ENTCS 2006»
14 years 10 months ago
Parallel Assignments in Software Model Checking
In this paper we investigate how formal software verification systems can be improved by utilising parallel assignment in weakest precondition computations.
Murray Stokely, Sagar Chaki, Joël Ouaknine
ENTCS
2006
130views more  ENTCS 2006»
14 years 10 months ago
LSC Verification for UML Models with Unbounded Creation and Destruction
The approaches to automatic formal verification of UML models known up to now require a finite bound on the number of objects existing at each point in time. In [4] we have observ...
Bernd Westphal