858 search results - page 87 / 172 » Formal Verification of Digital Systems |
100
click to vote
IWPSE
2010
IEEE
14 years 9 months ago
2010
IEEE
We describe our experiences with the process of designing a domain-specific language (DSL) and corresponding model transformations. The simultaneous development of the language an...
POPL
2010
ACM
15 years 8 months ago
2010
ACM
This paper describes a novel technique for the synthesis of imperative programs. Automated program synthesis has the potential to make programming and the design of systems easier...
110
click to vote
JSS
2010
14 years 5 months ago
2010
Architectural description languages are a useful tool for modeling complex systems at a high level of abstraction. If based on formal methods, they can also serve for enabling the...
ACSC
2004
IEEE
15 years 2 months ago
2004
IEEE
An approach to system verification is described in which design artefacts produced during forward engineering are automatically compared to corresponding artefacts produced during...
DAC
2003
ACM
15 years 12 months ago
2003
ACM
Verification of system designs continues to be a major challenge today. Simulation remains the primary tool for making sure that implementations perform as they should. We present...