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» Formal Verification of Digital Systems
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IFIP13
2004
15 years 3 months ago
Formal Verification and Validation of Interactive Systems Specifications
: This paper proposes a development process for interactive systems based both on verification and validation methods. Our approach is formal and use at first the B Method. We show...
Yamine Aït Ameur, Benoit Breholée, Pat...
FLAIRS
2000
15 years 3 months ago
Verification of Cooperating Systems - An Approach Based on Formal Languages
Behaviour of systems is described by formal languages: the sets of all sequences of actions. Regarding ion, alphabetic language homomorphisms are compute abstract behaviours. To a...
Peter Ochsenschläger, Jürgen Repp, Rolan...
FDL
2007
IEEE
15 years 5 months ago
Transactor-based Formal Verification of Real-time Embedded Systems
With the increasing complexity of today's embedded systems, there is a need to formally verify such designs at mixed abstraction levels. This is needed if some compoe describ...
Daniel Karlsson, Petru Eles, Zebo Peng
HASE
2008
IEEE
15 years 1 months ago
Aiding Modular Design and Verification of Safety-Critical Time-Triggered Systems by Use of Executable Formal Specifications
Designing safety-critical systems is a complex process, and especially when the design is carried out at different f abstraction where the correctness of the design at one level i...
Kohei Sakurai, Péter Bokor, Neeraj Suri
DFG
2004
Springer
15 years 5 months ago
Modeling and Formal Verification of Production Automation Systems
This paper presents the real-time model checker RAVEN and related theoretical background. RAVEN augments the efficiency of traditional symbolic model checking with possibilities to...
Jürgen Ruf, Roland J. Weiss, Thomas Kropf, Wo...