858 search results - page 96 / 172 » Formal Verification of Digital Systems |
SIMUTOOLS
2008
15 years 14 days ago
2008
Model checking is a suitable formal technique to analyze parallel programs' execution in an industrial context because automated tools can be designed and operated with very ...
101
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FORMATS
2010
Springer
14 years 9 months ago
2010
Springer
Abstract. We consider temporal logic formulae specifying constraints in continuous time and space on the behaviors of continuous and hybrid dynamical system admitting uncertain par...
100
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WWW
2004
ACM
15 years 11 months ago
2004
ACM
Complex Semantic Web (SW) services may have intricate data state, autonomous process behavior and concurrent interactions. The design of such SW service systems requires precise a...
EMSOFT
2006
Springer
15 years 2 months ago
2006
Springer
We report on a case study in which the model checker Uppaal is used to formally model parts of Zeroconf, a protocol for dynamic configuration of IPv4 link-local addresses that has...
110
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FDL
2007
IEEE
15 years 5 months ago
2007
IEEE
SystemVerilog encapsulates both design description and verification properties in one language and provides a unified environment for engineers who have the formidable challenge o...