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» Formal Verification of Digital Systems
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ETFA
2005
IEEE
15 years 3 months ago
Reuse of components in formal modeling and verification of distributed control systems
This paper describes formal modeling and verification of automation systems from the system engineering point of view. Reuse of model components is the key issue in order to bring...
Valeriy Vyatkin, Hans-Michael Hanisch
IEE
2008
117views more  IEE 2008»
14 years 9 months ago
Formal verification of systems with an unlimited number of components
1 2 3 In many real component-based systems and patterns of component interaction, there can be identified a stable part (like control component, server, instance handler) and a nu...
Pavlína Vareková, Barbora Zimmerova,...
HYBRID
1998
Springer
15 years 2 months ago
Formal Verification of Safety-Critical Hybrid Systems
This paper investigates how formal techniques can be used for the analysis and verification of hybrid systems [1,5,7,16] -- systems involving both discrete and continuous behavior....
Carolos Livadas, Nancy A. Lynch
ISCAS
2003
IEEE
135views Hardware» more  ISCAS 2003»
15 years 3 months ago
Formal verification of LTL formulas for SystemC designs
To handle today’s complexity, modern circuits and systems be specified at a high level of abstraction. Recently, SystemC has been proposed as a language that allows a fast on o...
Daniel Große, Rolf Drechsler
ICCS
2007
Springer
15 years 2 months ago
Formal Verification of Analog and Mixed Signal Designs in Mathematica
In this paper, we show how symbolic algebra in Mathematica can be used to formally verify analog and mixed signal designs. The verification methodology is based on combining induct...
Mohamed H. Zaki, Ghiath Al Sammane, Sofiène...