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VLSID
2002
IEEE
177views VLSI» more  VLSID 2002»
15 years 10 months ago
RTL-Datapath Verification using Integer Linear Programming
Satisfiability of complex word-level formulas often arises as a problem in formal verification of hardware designs described at the register transfer level (RTL). Even though most...
Raik Brinkmann, Rolf Drechsler
ISOLA
2004
Springer
15 years 3 months ago
A Formal Analysis of Bluetooth Device Discovery
Abstract. This paper presents a formal analysis of the device discovery phase of the Bluetooth wireless communication protocol. The performance of this process is the result of a c...
Marie Duflot, Marta Z. Kwiatkowska, Gethin Norman,...
FMCAD
2008
Springer
14 years 11 months ago
BackSpace: Formal Analysis for Post-Silicon Debug
Post-silicon debug is the problem of determining what's wrong when the fabricated chip of a new design behaves incorrectly. This problem now consumes over half of the overall ...
Flavio M. de Paula, Marcel Gort, Alan J. Hu, Steve...
CDC
2010
IEEE
141views Control Systems» more  CDC 2010»
14 years 4 months ago
Using computer games for hybrid systems controller synthesis
Abstract-- We propose a formal method for feedback controller synthesis using interactive computer programs with graphical interface (in short, computer games). The main theoretica...
A. Agung Julius, Sina Afshari
FMCAD
2004
Springer
15 years 1 months ago
Bloom Filters in Probabilistic Verification
Abstract. Probabilistic techniques for verification of finite-state transition systems offer huge memory savings over deterministic techniques. The two leading probabilistic scheme...
Peter C. Dillinger, Panagiotis Manolios