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DAC
2006
ACM
15 years 10 months ago
Early cutpoint insertion for high-level software vs. RTL formal combinational equivalence verification
Ever-growing complexity is forcing design to move above RTL. For example, golden functional models are being written as clearly as possible in software and not optimized or intend...
Xiushan Feng, Alan J. Hu
ICTAI
1997
IEEE
15 years 1 months ago
GA-Based Performance Analysis of Network Protocols
This paper tackles the problem of analyzing the correctness and performance of a computer network protocol. Given the complexity of the problem, no currently used technique is abl...
Mario Baldi, Fulvio Corno, Maurizio Rebaudengo, Gi...
CCECE
2006
IEEE
15 years 3 months ago
A Formal CSP Framework for Message-Passing HPC Programming
To help programmers of high-performance computing (HPC) systems avoid communication-related errors, we employ a formal process algebra, Communicating Sequential Processes (CSP), w...
John D. Carter, William B. Gardner
ICCAD
1994
IEEE
65views Hardware» more  ICCAD 1994»
15 years 1 months ago
Incremental formal design verification
Language containment is a method for design verification that involves checking if the behavior of the system to be verified is a subset of the behavior of the specifications (pro...
Gitanjali Swamy, Robert K. Brayton
DAC
2009
ACM
15 years 1 months ago
Fast vectorless power grid verification using an approximate inverse technique
Power grid verification in modern integrated circuits is an integral part of early system design where adjustments can be most easily incorporated. In this work, we describe an ea...
Nahi H. Abdul Ghani, Farid N. Najm