176 search results - page 5 / 36 » Formal Verification of Gate-Level Computer Systems |
CONCUR
2006
Springer
15 years 3 months ago
2006
Springer
One of the advantages of temporal-logic model-checking tools is their ability to accompany a negative answer to the correctness query by a counterexample to the satisfaction of the...
129
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CCECE
2006
IEEE
15 years 5 months ago
2006
IEEE
To help programmers of high-performance computing (HPC) systems avoid communication-related errors, we employ a formal process algebra, Communicating Sequential Processes (CSP), w...
113
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AINA
2003
IEEE
15 years 3 months ago
2003
IEEE
Condition Data Flow Diagrams (CDFDs) are a formalized notation resulting from the integration of Yourdon Data Flow Diagrams, Petri Nets, and pre-post notation. They are used in th...
CADE
2008
Springer
15 years 12 months ago
2008
Springer
Abstract. Operating-system verification gains increasing research interest. The complexity of such systems is, however, challenging and many endeavors are limited in some respect: ...
ICCAD
1994
IEEE
15 years 3 months ago
1994
IEEE
Language containment is a method for design verification that involves checking if the behavior of the system to be verified is a subset of the behavior of the specifications (pro...