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» Formal Verification of Security Model Using SPR Tool
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SECURWARE
2008
IEEE
16 years 15 days ago
Formal Modeling of Authentication in SIP Registration
The Session Initiation Protocol (SIP) is increasingly used as a signaling protocol for administrating Voice over IP (VoIP) phone calls. SIP can be configured in several ways so t...
Anders Moen Hagalisletto, Lars Strand
FMCAD
2008
Springer
15 years 7 months ago
Verifying an Arbiter Circuit
Abstract--This paper presents the verification of an asynchronous arbiter modeled at the circuit level with non-linear ordinary differential equations. We use Brockett's annul...
Chao Yan, Mark R. Greenstreet
192
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CODES
2008
IEEE
15 years 8 months ago
Model checking SystemC designs using timed automata
SystemC is widely used for modeling and simulation in hardware/software co-design. Due to the lack of a complete formal semantics, it is not possible to verify SystemC designs. In...
Paula Herber, Joachim Fellmuth, Sabine Glesner
DFG
2004
Springer
15 years 10 months ago
Verification of PLC Programs Given as Sequential Function Charts
Programmable Logic Controllers (PLC) are widespread in the manufacturing and processing industries to realize sequential procedures and to avoid safety-critical states. For the spe...
Nanette Bauer, Sebastian Engell, Ralf Huuck, Sven ...
188
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FORMATS
2007
Springer
15 years 10 months ago
Partial Order Reduction for Verification of Real-Time Components
Abstract. We describe a partial order reduction technique for a realtime component model. Components are described as timed automata with data ports, which can be composed in stati...
John Håkansson, Paul Pettersson