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DATE
2005
IEEE
164views Hardware» more  DATE 2005»
15 years 7 months ago
Automated Synthesis of Assertion Monitors using Visual Specifications
Automated synthesis of monitors from high-level properties plays a significant role in assertion-based verification. We present here a methodology to synthesize assertion monitors...
Ambar A. Gadkari, S. Ramesh
FM
2003
Springer
174views Formal Methods» more  FM 2003»
15 years 7 months ago
Model-Checking TRIO Specifications in SPIN
We present a novel application on model checking through SPIN as a means for verifying purely descriptive specifications written in TRIO, a first order, linear-time temporal logic ...
Angelo Morzenti, Matteo Pradella, Pierluigi San Pi...
EUROMICRO
1996
IEEE
15 years 6 months ago
A Graph Rewriting Approach for Transformational Design of Digital Systems
Transformational design integrates design and verification. It combines "correctness by construciion" and design creativity by the use ofpre-proven behaviour preserving ...
Corrie Huijs
FMCAD
2009
Springer
15 years 5 months ago
Generalized, efficient array decision procedures
Abstract--The theory of arrays is ubiquitous in the context of software and hardware verification and symbolic analysis. The basic array theory was introduced by McCarthy and allow...
Leonardo Mendonça de Moura, Nikolaj Bj&osla...
ICFEM
2007
Springer
15 years 5 months ago
Testing for Refinement in CSP
Abstract. CSP is a well-established formalism for modelling and verification of concurrent reactive systems based on refinement. Consolidated denotational models and an effective t...
Ana Cavalcanti, Marie-Claude Gaudel