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DAC
1997
ACM
15 years 3 months ago
Formal Verification of a Superscalar Execution Unit
Abstract. Many modern systems are designed as a set of interconnected reactive subsystems. The subsystem verification task is to verify an implementation of the subsystem against t...
Kyle L. Nelson, Alok Jain, Randal E. Bryant
CADE
2007
Springer
16 years 2 days ago
Formal Device and Programming Model for a Serial Interface
Abstract. The verification of device drivers is essential for the pervasive verification of an operating system. To show the correctness of device drivers, devices have to be forma...
Eyad Alkassar, Mark A. Hillebrand, Steffen Knapp, ...
ICCS
2007
Springer
15 years 6 months ago
Equivalent Semantic Translation from Parallel DEVS Models to Time Automata
Dynamic reconfigurable simulation based on Discrete Event System Specification (DEVS) requires efficient verification of simulation models. Traditional verification method of DEVS ...
Shoupeng Han, Kedi Huang
TCAD
2008
181views more  TCAD 2008»
14 years 11 months ago
A Survey of Automated Techniques for Formal Software Verification
The quality and the correctness of software is often the greatest concern in electronic systems. Formal verification tools can provide a guarantee that a design is free of specific...
Vijay D'Silva, Daniel Kroening, Georg Weissenbache...
JOT
2007
169views more  JOT 2007»
14 years 11 months ago
Translating AUML Diagrams into Maude Specifications: A Formal Verification of Agents Interaction Protocols
Agents Interaction Protocols (AIPs) play a crucial role in multi-agents systems development. They allow specifying sequences of messages between agents. Major proposed protocols s...
Farid Mokhati, Noura Boudiaf, Mourad Badri, Linda ...