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ATVA
2009
Springer
141views Hardware» more  ATVA 2009»
15 years 3 months ago
Formal Verification for High-Assurance Behavioral Synthesis
We present a framework for certifying hardware designs generated through behavioral synthesis, by using formal verification to certify the associated synthesis transformations. We ...
Sandip Ray, Kecheng Hao, Yan Chen, Fei Xie, Jin Ya...
POPL
2008
ACM
16 years 2 days ago
Formal verification of translation validators: a case study on instruction scheduling optimizations
Translation validation consists of transforming a program and a posteriori validating it in order to detect a modification of its semantics. This approach can be used in a verifie...
Jean-Baptiste Tristan, Xavier Leroy
IJIT
2004
15 years 1 months ago
Formal Verification of a Multicast Protocol In Mobile Networks
As computer network technology becomes increasingly complex, it becomes necessary to place greater requirements on the validity of developing standards and the resulting technology...
Mohammad Reza Matash Borujerdi, S. M. Mirzababaei
FORMATS
2007
Springer
15 years 3 months ago
Combining Formal Verification with Observed System Execution Behavior to Tune System Parameters
Resource limited DRE (Distributed Real-time Embedded) systems can benefit greatly from dynamic adaptation of system parameters. We propose a novel approach that employs iterative t...
Minyoung Kim, Mark-Oliver Stehr, Carolyn L. Talcot...
CAISE
2007
Springer
15 years 3 months ago
Formalization and Verification of EPCs with OR-Joins Based on State and Context
The semantics of the OR-join in business process modeling languages like EPCs or YAWL have been discussed for a while. Still, the existing solutions suffer from at least one of two...
Jan Mendling, Wil M. P. van der Aalst