1129 search results - page 27 / 226 » Formal Verification of Websites |
JAVACARD
2000
15 years 3 months ago
2000
Abstract This note discusses a verification in PVS of the AID (Application Identifier) class from JavaCard's API. The properties that are verified are formulated in the interf...
ICCAD
2009
IEEE
14 years 9 months ago
2009
IEEE
Boolean satisfiability (SAT) based methods have traditionally been popular for formally verifying properties for digital circuits. We present a novel methodology for formulating a...
100
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FLAIRS
2000
15 years 1 months ago
2000
The paper presents a survey of the VSE system, a kind of CASE-tool for formal software development. It is a summary of a tutorial presentation describing methodology, formalisms, ...
101
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CONCUR
2006
Springer
15 years 3 months ago
2006
Springer
One of the advantages of temporal-logic model-checking tools is their ability to accompany a negative answer to the correctness query by a counterexample to the satisfaction of the...
106
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ICCD
2004
IEEE
15 years 8 months ago
2004
IEEE
Compared are different methods for evaluation of formulas expressing microprocessor correctness in the logic of Equality with Uninterpreted Functions and Memories (EUFM) by transl...