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DATE
2010
IEEE
168views Hardware» more  DATE 2010»
15 years 4 months ago
Formal verification of analog circuits in the presence of noise and process variation
We model and verify analog designs in the presence of noise and process variation using an automated theorem prover, MetiTarski. Due to the statistical nature of noise, we propose ...
Rajeev Narayanan, Behzad Akbarpour, Mohamed H. Zak...
GLVLSI
1999
IEEE
90views VLSI» more  GLVLSI 1999»
15 years 4 months ago
Formal Verification of Tree-Structured Carry-Lookahead Adders
Sae Hwan Kim, Shiu-Kai Chin
ASIAN
1999
Springer
89views Algorithms» more  ASIAN 1999»
15 years 4 months ago
Formal Verification of the MCS List-Based Queuing Lock
Kazuhiro Ogata, Kokichi Futatsugi
CAV
1998
Springer
86views Hardware» more  CAV 1998»
15 years 4 months ago
Formal Verification of Out-of-Order Execution Using Incremental Flushing
We present a two-part approach for verifying out-of-order execution. First, the complexity of out-of-order issue and scheduling is handled by creating der abstraction of the out-of...
Jens U. Skakkebæk, Robert B. Jones, David L....