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ICCAD
1996
IEEE
93views Hardware» more  ICCAD 1996»
15 years 6 months ago
VERILAT: verification using logic augmentation and transformations
This paper presents a new framework for formal logic verification. What is depicted here is fundamentally different from previous approaches. In earlier approaches, the circuit is ...
Dhiraj K. Pradhan, Debjyoti Paul, Mitrajit Chatter...
ESOP
2010
Springer
15 years 5 months ago
TRX: A Formally Verified Parser Interpreter
Parsing is an important problem in computer science and yet surprisingly little attention has been devoted to its formal verification. In this paper, we present TRX: a parser inter...
Adam Koprowski, Henri Binsztok
ENTCS
2008
135views more  ENTCS 2008»
15 years 2 months ago
Formal Specification Generation from Requirement Documents
Automatic generation of formal specifications from requirement reduces cost and complexity of formal models creation. Thus, the generated formal model brings the possibility to ca...
Gustavo Cabral, Augusto Sampaio
COMCOM
2000
82views more  COMCOM 2000»
15 years 1 months ago
Experience with RT-LOTOS, a temporal extension of the LOTOS formal description technique
This paper is devoted to the presentation of the RT-LOTOS formal description technique, which is a formalism suited for applications where concurrency, complex synchronization pat...
Jean-Pierre Courtiat, C. A. S. Santos, Christophe ...
DSD
2005
IEEE
116views Hardware» more  DSD 2005»
15 years 7 months ago
Validation of Embedded Systems Using Formal Method Aided Simulation
This paper proposes a validation approach, based on simulation, which addresses problems related to both state space explosion of formal methods and low coverage of informal metho...
Daniel Karlsson, Petru Eles, Zebo Peng