1446 search results - page 270 / 290 » Formal analysis of hardware requirements |
106
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IWMM
1998
Springer
15 years 4 months ago
1998
Springer
Many high-level language compilers generate C code and then invoke a C compiler for code generation. To date, most of these compilers link the resulting code against a conservativ...
MICRO
1997
IEEE
15 years 4 months ago
1997
IEEE
We revisit memory hierarchy design viewing memory as an inter-operation communication agent. This perspective leads to the development of novel methods of performing inter-operati...
102
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CAV
2006
Springer
15 years 3 months ago
2006
Springer
Example Guided Abstraction Refinement (CEGAR) [6] framework. A number of wellengineered software model-checkers are available, e.g., SLAM [1] and BLAST [12]. Why build another one?...
121
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ISCA
1995
IEEE
15 years 3 months ago
1995
IEEE
For many programs, especially integer codes, untolerated load instruction latencies account for a significant portion of total execution time. In this paper, we present the desig...
MICRO
2010
IEEE
14 years 9 months ago
2010
IEEE
The ever-increasing importance of main memory latency and bandwidth is pushing CMPs towards caches with higher capacity and associativity. Associativity is typically improved by in...