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FMCAD
2009
Springer
15 years 10 months ago
Debugging formal specifications using simple counterstrategies
Robert Könighofer, Georg Hofferek, Roderick B...
FMCAD
2009
Springer
15 years 10 months ago
Formal verification of correctness and performance of random priority-based arbiters
Krishnan Kailas, Viresh Paruthi, Brian Monwai
FTRTFT
1998
Springer
15 years 8 months ago
Towards a Formal Semantics of Verilog Using Duration Calculus
Gerardo Schneider, Qiwen Xu