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» Formal testing from timed finite state machines
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ACSAC
2005
IEEE
15 years 7 months ago
Automated and Safe Vulnerability Assessment
As the number of system vulnerabilities multiplies in recent years, vulnerability assessment has emerged as a powerful system security administration tool that can identify vulner...
Fanglu Guo, Yang Yu, Tzi-cker Chiueh
EMSOFT
2006
Springer
15 years 5 months ago
Analysis of the zeroconf protocol using UPPAAL
We report on a case study in which the model checker Uppaal is used to formally model parts of Zeroconf, a protocol for dynamic configuration of IPv4 link-local addresses that has...
Biniam Gebremichael, Frits W. Vaandrager, Miaomiao...
ICSM
2009
IEEE
15 years 8 months ago
A theoretical and empirical study of EFSM dependence
Dependence analysis underpins many activities in software maintenance such as comprehension and impact analysis. As a result, dependence has been studied widely for programming la...
Kelly Androutsopoulos, Nicolas Gold, Mark Harman, ...
EURODAC
1994
IEEE
110views VHDL» more  EURODAC 1994»
15 years 5 months ago
Symbolic exploration of large circuits with enhanced forward/backward traversals
Symbolic state space exploration techniques for Finite State Machines (FSMs) are a major recent result in CAD for VLSI. Most of them are exact and based on forward traversal, but ...
Gianpiero Cabodi, Paolo Camurati, Stefano Quer
ICML
2004
IEEE
16 years 2 months ago
Learning and discovery of predictive state representations in dynamical systems with reset
Predictive state representations (PSRs) are a recently proposed way of modeling controlled dynamical systems. PSR-based models use predictions of observable outcomes of tests that...
Michael R. James, Satinder P. Singh