299 search results - page 24 / 60 » Formal verification of analog designs using MetiTarski |
111
click to vote
ICFEM
1998
Springer
15 years 3 months ago
1998
Springer
Studying industrial systems by simulation enables the designer to study the dynamic behaviour and to determine some characteristics of the system. Unfortunately, simulation also h...
SIGSOFT
2003
ACM
16 years 12 days ago
2003
ACM
This paper describes a compositional proof strategy for verifying properties of requirements specifications. The proof strategy, which may be applied using either a model checker ...
125
click to vote
TII
2008
14 years 11 months ago
2008
Abstract--Safety analysis in Systems Engineering (SE) processes, as usually implemented, rarely relies on formal methods such as model checking since such techniques, however power...
116
click to vote
SIGSOFT
2007
ACM
16 years 13 days ago
2007
ACM
Automated verification is a technique for establishing if certain properties, usually expressed in temporal logic, hold for a system model. The model can be defined using a high-l...
104
click to vote
ISSRE
2000
IEEE
15 years 4 months ago
2000
IEEE
The Unified Modeling Language, UML, is the objectoriented notation adopted as the standard for objectoriented Analysis and Design by the Object Management Group. This paper report...