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» Formal verification of analog designs using MetiTarski
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SIGSOFT
2005
ACM
16 years 13 days ago
Towards a unified formal model for supporting mechanisms of dynamic component update
The continuous requirements of evolving a delivered software system and the rising cost of shutting down a running software system are forcing researchers and practitioners to fin...
Junrong Shen, Xi Sun, Gang Huang, Wenpin Jiao, Yan...
ASPDAC
2007
ACM
79views Hardware» more  ASPDAC 2007»
15 years 3 months ago
Challenges to Accuracy for the Design of Deep-Submicron RF-CMOS Circuits
- Two challenges for the accurate prediction of GHz CMOS analog/RF building blocks are presented. Challenging the usage of new compact MOSFET models enhances the simulation accurac...
S. Yoshitomi
ICSE
2007
IEEE-ACM
15 years 11 months ago
Plug-and-Play Architectural Design and Verification
Abstract. In software architecture, components represent the computational units of a system and connectors represent the interactions among those units. Making decisions about the...
Shangzhu Wang, George S. Avrunin, Lori A. Clarke
CAISE
2010
Springer
15 years 24 days ago
Design and Verification of Instantiable Compliance Rule Graphs in Process-Aware Information Systems
For enterprises it has become crucial to check compliance of their business processes with certain rules such as medical guidelines or financial regulations. When automating compli...
Linh Thao Ly, Stefanie Rinderle-Ma, Peter Dadam
FMCAD
2008
Springer
15 years 1 months ago
Going with the Flow: Parameterized Verification Using Message Flows
A message flow is a sequence of messages sent among processors during the execution of a protocol, usually illustrated with something like a message sequence chart. Protocol design...
Murali Talupur, Mark R. Tuttle