299 search results - page 30 / 60 » Formal verification of analog designs using MetiTarski |
FMCAD
2008
Springer
15 years 1 months ago
2008
Springer
Performing synthesis and verification in isolation has two undesirable consequences: (1) verification runs the risk of becoming intractable, and (2) strong sequential optimization...
115
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ICFEM
2010
Springer
14 years 10 months ago
2010
Springer
Abstract. Due to new emerging areas in the communication field there is a constant need for the design of novel communication protocols. This demands techniques for a rapid and eff...
103
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EUROMICRO
1996
IEEE
15 years 3 months ago
1996
IEEE
Transformational design integrates design and verification. It combines "correctness by construciion" and design creativity by the use ofpre-proven behaviour preserving ...
DAC
2002
ACM
16 years 20 days ago
2002
ACM
A central problem in functional verification is to check that a circuit block is producing correct outputs while enforcing that the environment is providing legal inputs. To attac...
MICRO
2008
IEEE
14 years 11 months ago
2008
IEEE
Verification of chip multiprocessor memory systems remains challenging. While formal methods have been used to validate protocols, simulation is still the dominant method used to ...