299 search results - page 31 / 60 » Formal verification of analog designs using MetiTarski |
TSMC
2010
14 years 6 months ago
2010
Computer system reliability is conventionally modeled and analyzed using techniques such as fault tree analysis (FTA) and reliability block diagrams (RBD), which provide static rep...
DAC
2007
ACM
16 years 21 days ago
2007
ACM
tive Guidance Strategy for Abstraction-Guided Simulation Flavio M. De Paula Alan J. Hu Department of Computer Science, University of British Columbia, {depaulfm, ajh}@cs.ubc.ca D...
FDL
2008
IEEE
15 years 1 months ago
2008
IEEE
In this paper, we propose the design methodology for communication channel templates from formal specification to RTL description. In this flow, design and verification start from...
ASE
2008
14 years 11 months ago
2008
Model checkers were originally developed to support the formal verification of high-level design models of distributed system designs. Over the years, they have become unmatched in...
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VLSID
2002
IEEE
16 years 2 days ago
2002
IEEE
Directed test program-based verification or formal verification methods are usually quite ineffective on large cachecoherent, non-uniform memory access (CC-NUMA) multiprocessors b...