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» Formal verification of analog designs using MetiTarski
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DAC
2009
ACM
16 years 22 days ago
Efficient SAT solving for non-clausal formulas using DPLL, graphs, and watched cuts
Boolean satisfiability (SAT) solvers are used heavily in hardware and software verification tools for checking satisfiability of Boolean formulas. Most state-of-the-art SAT solver...
Himanshu Jain, Edmund M. Clarke
ICSE
2008
IEEE-ACM
16 years 16 days ago
Calysto: scalable and precise extended static checking
Automatically detecting bugs in programs has been a long-held goal in software engineering. Many techniques exist, trading-off varying levels of automation, thoroughness of covera...
Domagoj Babic, Alan J. Hu
ICFEM
1997
Springer
15 years 3 months ago
Formally Specifying and Verifying Real-Time Systems
A real-time computer system is a system that must perform its functions within specified time bounds. These systems are generally characterized by complex interactions with the en...
Richard A. Kemmerer
RE
2008
Springer
14 years 11 months ago
Requirements Capture with RCAT
NASA spends millions designing and building spacecraft for its missions. The dependence on software is growing as spacecraft become more complex. With the increasing dependence on...
Margaret H. Smith, Klaus Havelund
FMICS
2006
Springer
15 years 3 months ago
Verified Design of an Automated Parking Garage
Parking garages that stow and retrieve cars automatically are becoming viable solutions for parking shortages. However, these are complex systems and a number of severe incidents i...
Aad Mathijssen, A. Johannes Pretorius