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» Formal verification of analog designs using MetiTarski
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DAC
1994
ACM
15 years 3 months ago
Error Diagnosis for Transistor-Level Verification
This paper describes a diagnosis technique for locating design errors in circuit implementations which do not match their functional specification. The method efficiently propagat...
Andreas Kuehlmann, David Ihsin Cheng, Arvind Srini...
AMAST
2008
Springer
15 years 1 months ago
Verification of Java Programs with Generics
Several proof systems allow the formal verification of Java programs, and a specification language was specifically designed for Java. However, none of these systems support generi...
Kurt Stenzel, Holger Grandy, Wolfgang Reif
AIEDAM
2002
100views more  AIEDAM 2002»
14 years 11 months ago
Drawing marks, acts, and reacts: Toward a computational sketching interface for architectural design
Architects use sketching and diagramming in their design process to perform functional reasoning, formal arrangements, analogy transfer, structure mapping, and knowledge acquisiti...
Ellen Yi-Luen Do
CSEE
2000
Springer
15 years 4 months ago
Technology Transfer Issues for Formal Methods of Software Specification
Accurate and complete requirements specifications are crucial for the design and implementation of high-quality software. Unfortunately, the articulation and verification of softw...
Ken Abernethy, John C. Kelly, Ann E. Kelley Sobel,...
CADE
2008
Springer
16 years 1 days ago
Exploring Model-Based Development for the Verification of Real-Time Java Code
Many safety- and security-critical systems are real-time systems and, as a result, tools and techniques for verifying real-time systems are extremely important. Simulation and test...
Niusha Hakimipour, Paul A. Strooper, Roger Duke