299 search results - page 36 / 60 » Formal verification of analog designs using MetiTarski |
CAV
2009
Springer
16 years 8 days ago
2009
Springer
Recent development on distributed systems has shown that a variety of fairness constraints (some of which are only recently defined) play vital roles in designing self-stabilizing ...
APSEC
2004
IEEE
15 years 3 months ago
2004
IEEE
To formalize a software process, its important aspects must be extracted as a model. Many processes are used repeatedly, and the ability to automate a process is also desired. One...
DAC
2003
ACM
16 years 21 days ago
2003
ACM
SAT-based decision procedures for quantifier-free fragments of firstorder logic have proved to be useful in formal verification. These decision procedures are either based on enco...
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FMOODS
2006
15 years 1 months ago
2006
In this paper we describe an application of the theory of graph transformations to the practise of language design. In particular, we have defined the static and dynamic semantics ...
DATE
2005
IEEE
15 years 5 months ago
2005
IEEE
Automated synthesis of monitors from high-level properties plays a significant role in assertion-based verification. We present here a methodology to synthesize assertion monitors...