299 search results - page 5 / 60 » Formal verification of analog designs using MetiTarski |
130
Voted
DAC
1997
ACM
15 years 5 months ago
1997
ACM
We present our experiences with the formal verification of an automotive chip used to control the safety features in a car. We used a BDD based model checker in our work. We descr...
127
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ICCAD
2002
IEEE
15 years 10 months ago
2002
IEEE
In this paper we present an advanced functional extraction tool for automatic generation of high-level RTL from switch-level circuit netlist representation. The tool is called FEV...
DATE
2006
IEEE
15 years 7 months ago
2006
IEEE
—In this paper we describe a methodology to measure exactly the quality of fault-tolerant designs by combining faultinjection in high level design (HLD) descriptions with a forma...
FDL
2004
IEEE
15 years 5 months ago
2004
IEEE
In this paper, we introduce a layout description and generation model, GBLD, based on the notions and elements of L-systems and context-free grammars. Our layout model is compatib...
108
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DATE
2003
IEEE
15 years 7 months ago
2003
IEEE
Today’s mobile communication systems use sophisticated signal processing to achieve high transmission rates. Therefore a high complexity in the digital system part as well as ve...